pins = "gpio40";
};
};
+
+ ephy_rst: reset-controller@3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial@10000100 {
reg = <0x10080000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 3>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
pins = "dsl_gpio9";
};
};
+
+ ephy_rst: reset-controller@3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial@10000180 {
<&timer_clk BCM63268_TCLK_GPHY1>;
resets = <&periph_rst BCM63268_RST_ENETSW>,
- <&periph_rst BCM63268_RST_EPHY>,
- <&periph_rst BCM63268_RST_GPHY>;
+ <&periph_rst BCM63268_RST_EPHY>;
power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
reg = <0x10700000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&periph_rst BCM63268_RST_GPHY>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
pins = "usb_port1";
};
};
+
+ ephy_rst: reset-controller@3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial@10000100 {
reg = <0x10e00000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 3>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
pins = "nand_grp";
};
};
+
+ ephy_rst: reset-controller@3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
uart0: serial@10000100 {
reg = <0x10e00000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 0>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 1>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 2>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 3>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};
pins = "uart1_grp";
};
};
+
+ ephy_rst: reset-controller@3c {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0x3c 0x4>;
+ #reset-cells = <1>;
+ };
};
leds: led-controller@100000d0 {
reg = <0x10f00000 0x8000>;
big-endian;
+ brcm,gpio-ctrl = <&gpio_cntl>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+
+ resets = <&ephy_rst 6>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
+
+ resets = <&ephy_rst 7>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
+
+ resets = <&ephy_rst 8>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
+
+ resets = <&ephy_rst 9>;
+ reset-names = "phy";
+ reset-assert-us = <2000>;
+ reset-deassert-us = <2000>;
};
};